PAPA - Packed Arithmetic on a Prefix Adder for Multimedia Applications

This paper introduces PAPA: Packed Arithmetic on a Prefix Adder, a new approach to parallel prefix adder design that supports a wide variety of packed arithmetic computations, including packed add and subtract with saturation, packed rounded average, and packed absolute difference. The approach consists of altering the prefix adder cell logic equations to take advantage of a previously unused “don’t care” state. Logical Effort is employed to assess the delay of the new adder architecture by establishing the extra effort needed to select and drive the appropriate carry signal to the requisite sum sub-word. This adder will find applications in video processors and other multimedia-orientated processor chips that impl ement packed arithmetic operations. 1. Motivation Multimedia processor chips (and others) make much use of “packed” arithmetic operations in order to accelerate a variety of digital signal processing algorithms for consumer applications. In such arithmetic units, long wordlength numbers are optionally treated as several independent shorter wordlength numbers – for example, a 32-bit word may be treated as 2 separate 16-bit words or as 4 8-bit words. The main motivation for this mode of operation is to support SIMD processing with its associated advantages in the context of a conventional pipelined load-store processor architecture [1]. Moreover, a common arithmetic operation used in video processing is “absolute difference”, denoted A–B, and used widely in video motion estimation and prediction algorithms. Hence, a most valuable operation is a “packed absolute difference” operation, which returns the absolute differences of a several independent pairs of 8-bit pixel values simultaneously. Ordinarily, absolute differences are computed either by performing a subtraction operation followed by a separate “absolute value” operation, which returns the magnitude of a signed number, or by performing a comparison to order the operands followed by a subtraction in which the smaller operand is subtracted from the larger [2]. Instead of such two-step implementations, absolute differences can be obtained by computing both A–B and B–A, and using the signs of the two results to select the positive result [3]. However, this is wasteful and a better technique is sought. Recently, some authors have des cribed how absolute differences can be derived using a single prefix adder [4, 5], but have not extended this insight to packed arithmetic. Previously reProceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP’02) 1063-6862/02 $17.00 © 2002 IEEE ported implementations of packed arithmetic prefix adders include [6, 7], but neither of these proposals is able to support packed late increment operations, vital for computing absolute difference and rounded average instructions. A second valuable arithmetic option for media applications is saturated arithmetic, in which overflows and underflows do not cause exceptions but rather return pre-defined “saturation constants” [8]. Such constants should ideally be incorporated with little or no performance overhead since the integer adder is typically on the critical path that defines a processor’s clock rate. This paper describes how a prefix adder can be altered straightforwardly to support packed absolute difference and rounded average instructions as well as packed saturated arithmetic, and further describes how Logical Effort was employed to assess its performance potential. 2. Packed arithmetic on a parallel prefix adder 2.1 Prefix tree cell logic The parallel prefix carry-lookahead adder is a popular VLSI design technique that accelerates an n-bit addition by means of a parallel prefix tree [9]. A block diagram of a prefix adder is illustrated in Figure 1, where the adder is seen to consist of three blocks: input bit propagate, generate, and not kill cells; the prefix tree; output sum cells. The input cells derive the bit propagate, generate, and not kill signals respectively according to: p(i) = a(i) ⊕ b(i) ____ (1a) g(i) = a(i) ∧ b(i) ____ (1b) ¬k(i) = a(i) ∨ b(i) ____ (1c)